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vishay siliconix si8429db document number: 74399 s13-1847-rev.d, 19-aug-13 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com p-channel 1.2 v (g-s) mosfet features ? trenchfet ? power mosfet ? industry first 1.2 v rated mosfet ? ultra small micro foot ? chipscale packaging reduces footprint area, profile (0.62 mm) and on-resistance per footprint area ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? low threshold load switch for portable devices - low power consumption - increased battery life ? ultra low voltage load switch notes: a. based on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. refer to ipc/jedec (j-std -020), no manual or hand soldering. e. in this document, any reference to the case represents the body of the micro foot device and foot is the bump. product summary v ds (v) r ds(on) ( ? ) i d (a) a q g (typ.) - 8 0.035 at v gs = - 4.5 v - 11.7 21 nc 0.042 at v gs = - 2.5 v - 10.7 0.052 at v gs = - 1.8 v - 9.6 0.069 at v gs = - 1.5 v - 8.3 0.098 at v gs = - 1.2 v - 1.02 micro foot 3 2 41 s dd g b u mp s ide v ie w b a ck s ide v ie w device markin g : 8 429 xxx = d a te/lot tr a ce a b ility code 8 429 xxx orderin g information: si 8 429db-t1-e1 (lead (p b )-free and halogen-free) s g d p-channel mosfet absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 8 v gate-source voltage v gs 5 continuous drain current (t j = 150 c) t c = 25 c i d - 11.7 a t c = 70 c - 9.4 t a = 25 c - 7.8 b, c t a = 70 c - 6.3 b, c pulsed drain current i dm - 25 continuous source-drain diode current t c = 25 c i s - 5.7 t a = 25 c - 2.5 b, c maximum power dissipation t c = 25 c p d 6.25 w t c = 70 c 4 t a = 25 c 2.77 b, c t a = 70 c 1.77 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c package reflow conditions d ir/convection 260
vishay siliconix si8429db www.vishay.com 2 document number: 74399 s13-1847-rev.d, 19-aug-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. surface mounted on 1" x 1" fr4 board. b. maximum under steady stat e conditions is 85 c/w. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient a, b r thja 35 45 c/w maximum junction-to-foot (drain) steady state r thjf 16 20 specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 8 v v ds temperature coefficient ? v ds /t j i d = - 250 a - 7.5 mv/c v gs(th) temperature coefficient ? v gs(th) /t j - 2.2 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.35 - 0.8 v v ds = v gs , i d = - 5 ma - 0.6 gate-source leakage i gss v ds = 0 v, v gs = 5 v 100 na zero gate voltage drain current i dss v ds = 8 v, v gs = 0 v - 1 a v ds = - 8 v, v gs = 0 v, t j = 70 c - 10 on-state drain current a i d(on) v ds ?? 5 v, v gs = - 4.5 v - 5 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 1 a 0.029 0.035 ? v gs = - 2.5 v, i d = - 1 a 0.035 0.042 v gs = - 1.8 v, i d = - 1 a 0.043 0.052 v gs = - 1.5 v, i d = - 1 a 0.051 0.069 v gs = - 1.2 v, i d = - 1 a 0.065 0.098 forward transconductance a g fs v ds = - 4 v, i d = - 1 a 0.7 1.2 s dynamic b input capacitance c iss v ds = - 4 v, v gs = 0 v, f = 1 mhz 1640 pf output capacitance c oss 590 reverse transfer capacitance c rss 380 total gate charge q g v ds = - 4 v, v gs = - 5 v, i d = - 1 a 24 26 nc v ds = - 4 v, v gs = - 4.5 v, i d = 1 a 21 32 gate-source charge q gs 1.8 gate-drain charge q gd 3.7 gate resistance r g v gs = - 0.1 v, f = 1 mhz 22 ? tu r n - o n d e l ay t i m e t d(on) v dd = - 4 v, r l = 4 ? i d ? - 1 a, v gen = - 4.5 v, r g = 6 ? 12 20 ns rise time t r 25 40 turn-off delay time t d(off) 260 390 fall time t f 155 240
vishay siliconix si8429db document number: 74399 s13-1847-rev.d, 19-aug-13 www.vishay.com 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 2.5 a pulse diode forward current i sm - 25 body diode voltage v sd i s = - 1 a, v gs = 0 v - 0.7 - 1.1 v body diode reverse recovery time t rr i f = - 1 a, di/dt = 100 a/s, t j = 25 c 150 250 ns body diode reverse recovery charge q rr 150 230 nc reverse recovery fall time t a 57 ns reverse recovery rise time t b 93
vishay siliconix si8429db www.vishay.com 4 document number: 74399 s13-1847-rev.d, 19-aug-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current and gate voltage gate charge 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 v gs = 5 thr u 2 v 1 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 1.5 v ( e c n a t s i s e r - n o - r ) n o ( s d ) i d - drain c u rrent (a) 0.02 0.03 0.04 0.05 0.06 0.07 0.0 8 0 5 10 15 20 25 v gs = 2.5 v v gs = 4.5 v v gs = 1.2 v v gs = 1.5 v v gs = 1. 8 v 0 1 2 3 4 5 0 5 10 15 20 25 v ds = 4 v i d = 1 a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 5 10 15 20 25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 25 c t c = 125 c - 55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 0 500 1000 1500 2000 2500 01234567 8 c rss c oss c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0. 8 0.9 1.0 1.1 1.2 1.3 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v , 2.5 v , 1. 8 v , 1.5 v i d = 1 a t j - j u nction temperat u re (c) r ds(on) - on-resistance ( n ormalized)
vishay siliconix si8429db document number: 74399 s13-1847-rev.d, 19-aug-13 www.vishay.com 5 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage 1.0 1.4 1 10 20 0.0 0.2 0.4 0.6 0. 8 t j = 25 c t j = 150 c v sd - so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 1.2 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a t j - temperat u re (c) v gs(th) ( v ) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.02 0.03 0.04 0.05 0.06 0.07 0.0 8 012345 i d = 1 a v gs - gate-to-so u rce v oltage ( v ) r ds(on) - drain-to-so u rce on-resistance (m ) t a = 25 c t a = 125 c 0.001 0 40 8 0 60 10 time (s) 20 po w er ( w ) 0.01 0.1 1 100 600 safe operating area, junction-to-ambient 100 1 0 1 1 1 . 0 0.01 10 - drain c u rrent (a) i d 0.1 t a = 25 c single p u lse v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified p(t) = 10 dc i dm limited i d(on) limited b v dss limited p(t) = 1 p(t) = 0.1 p(t) = 0.01 p(t) = 0.001 p(t) = 0.0001 limited b y r ds(on) *
vishay siliconix si8429db www.vishay.com 6 document number: 74399 s13-1847-rev.d, 19-aug-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max.) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. current derating* 0 2 4 6 8 10 12 25 50 75 100 125 150 i d - drain c u rrent (a) t f - foot temperat u re (c) normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 600 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 72 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance
vishay siliconix si8429db document number: 74399 s13-1847-rev.d, 19-aug-13 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com package outline micro foot: 4-bump (0.8 mm pitch) notes (unless other wise specified): 1. laser mark on the silicon die back, coated with a thin metal. 2. bumps are sn/ag/cu. 3. non-solder mask defined copper landing pad. 4. the flat side of wafers is oriented at the bottom. notes: a. use millimeters as the primary measurement vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?74399 . b u mp n ote 2 8 429 xxx recommended l a nd m a rk on b a ck s ide of die s ilicon b di a merter e e a a 2 a 1 e s d e s e 4 x 0. 3 0 0. 3 1 n ote 3 s older m as k 0.40 dim. millimeters a inches min. max. min. max. a 0.600 0.650 0.0236 0.0256 a 1 0.260 0.290 0.0102 0.0114 a 2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 d 1.520 1.600 0.0598 0.0630 e 1.520 1.600 0.0598 0.0630 e 0.800 0.0315 s 0.360 0.400 0.0142 0.0157
an824 vishay siliconix document number: 71990 06-jan-03 www.vishay.com 1 pcb design and assembly guidelines for micro foot products johnson zhao introduction vishay siliconix?s micro foot product family is based on a wafer-level chip-scale packaging (wl-csp) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. micro foot products include power mosfets, analog switches, and power ics. for battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. for example, the 6 ? bump micro foot si8902edb common drain power mosfet, which measures just 1.6 mm x 2.4 mm, achieves the same performance as tssop ? 8 devices in a footprint that is 80% smaller and with a 50% lower height profile (figure 1). a micro foot analog switch, the 6 ? bump dg3000db, offers low charge injection and 1.4 w on ? resistance in a footprint measuring just 1.08 mm x 1.58 mm (figure 2). vishay siliconix micro foot products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. with proper attention to pcb and stencil design, the device will achieve reliable performance without underfill. the advantage of the device?s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, pdas, cellular phones, and notebook computers. this application note discusses the mechanical design and reliability of micro foot, and then provides guidelines for board layout, the assembly process, and the pcb rework process. figure 1. 3d view of micro foot products si8902db and si8900edb figure 2. outline of micro foot csp & analog switch dg3000db 0.18 ~ 0.25 321 a b 0.5 1.58 0.5 0.285 0.285 1.08
an824 vishay siliconix www.vishay.com 2 document number: 71990 06-jan-03 table 1 main parameters of solder bumps in micro foot designs micro foot csp mosfet micro foot?s design and reliability as a mechanical, electrical, and thermal connection between the device and pcb, the solder bumps of micro foot products are mounted on the top active surface of the die. table 1 shows the main parameters for solder bumps used in micro foot products. a silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. a green laser is used to mark the backside of the die without damaging it. reliability results for micro foot products mounted on a fr-4 board without underfill are shown in table 2. table 2 micro foot reliability results test condition c: ? 65 to 150 c ? 40 to 125 c c @ 15psi 100% humidity test board layout guidelines board materials . vishay siliconix micro foot products are designed to be reliable on most board types, including organic boards such as fr-4 or polyamide boards. the package qualification information is based on the test on 0.5-oz. fr-4 and polyamide boards with nsmd pad design. land patterns. two types of land patterns are used for surface-mount packages. solder mask defined (smd) pads have a solder mask opening smaller than the metal pad (figure 3), whereas on-solder mask defined (nsmd) pads have a metal pad smaller than the solder-mask opening (figure 4). nsmd is recommended for copper etch processes, since it provides a higher level of control compared to smd etch processes. a small-size nsmd pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the pcb. by contrast, smd pad definition introduces a stress concentration point near the solder mask on the pcb side that may result in solder joint cracking under extreme fatigue conditions. copper pads should be finished with an organic solderability preservative (osp) coating. for electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 m to avoid solder joint embrittlement. figure 3. smd figure 4. nsmd copper solder mask copper solder mask
an824 vishay siliconix document number: 71990 06-jan-03 www.vishay.com 3 board pad design. the landing-pad size for micro foot products is determined by the bump pitch as shown in table 3. the pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. table 3 dimensions of copper pad and solder mask opening in pcb and stencil aperture pitch copper pad solder mask opening stencil aperture 0.80 mm 0.01 mm 0.01 mm 0.01 mm in ciircle aperture 0.01 mm 0.01 mm 0.01 mm in square aperture assembly process micro foot products? surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (figure 5). figure 5. smt assembly process flow stencil design iincoming tape and reel inspection solder paste printing chip placement reflow solder joint inspection pack and ship stencil design . stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). the stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. in micro foot products, the stencil is 0.125- mm (5-mils) thick. the recommended apertures are shown in table 3 and are fabricated by laser cut. solder-paste printing. the solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. in micro foot products, the solder paste used is up78 no-clean eutectic 63 sn/37pb type3 or finer solder paste. chip pick-and-placement. micro foot products can be picked and placed with standard pick-and-place equipment. the recommended pick-and-place force is 150 g. though the part will self-center during solder reflow, the maximum placement of fset is 0.02 mm. reflow process . micro foot products can be assembled using standard smt reflow processes. similar to any other package, the thermal profile at specific board locations must be determined. nitrogen purge is recommended during reflow operation. figure 6 shows a typical reflow profile. 0 50 100 150 200 250 0 100 200 300 400 thermal profile time (seconds figure 6. reflow profile temperature ( c) pcb rework to replace micro foot products on pcb, the rework procedure is much like the rework process for a standard bga or csp, as long as the rework process duplicates the original reflow profile. the key steps are as follows: 1. remove the micro foot device using a convection nozzle to create localized heating similar to the original reflow profile. preheat from the bottom. 2. once the nozzle temperature is +190 c, use tweezers to remove the part to be replaced. 3. resurface the pads using a temperature-controlled soldering iron. 4. apply gel flux to the pad. 5. use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. 6. reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile.
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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